A Wide-Tracking Range Clock and Data Recovery Circuit
نویسندگان
چکیده
منابع مشابه
Low Jitter and Wide Band frequency Clock Recovery Circuit
Clock recovery circuits are used in data communication systems for the system synchronization. In general a PLL (Phase Locked Loop) circuit is used to extract the clock signal from the input data stream. The recovered clock signal is always jittered and have to be adjusted by using a dejitter circuit. Tracking these errors over an extended period of time determines the system stability. Sources...
متن کاملA 4-Gb/s CMOS Clock and Data Recovery Circuit Using 1=8-Rate Clock Technique
A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25m standard CMOS technology. The CDR circuit exploits 1 8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating fo...
متن کاملA 3.2Gb/s Clock and Data Recovery Circuit Without Reference Clock for a High-Speed Serial Data Link
A 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial link without the reference clock is described. The CDR has a phase and frequency detector (PD and FD), which incorporates a half-rate bang-bang type oversampling PD and a half-rate frequency detector that can achieve low-jitter operation and improve pull-in range. The PD of oversamping method finds a phase error by generati...
متن کاملA CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector
A clock and data recovery (CDR) circuit using a new halfrate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-μm N-well CMOS technique. Experimental r...
متن کاملA 3.125Gb/s Clock and Data Recovery Circuit Using 1/4-Rate Technique
This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in rang...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEEE Journal of Solid-State Circuits
سال: 2008
ISSN: 0018-9200
DOI: 10.1109/jssc.2007.914290